The new VEX coding scheme introduces a new set of code prefixes that extends the opcode space, allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 128 bits. Notably, the VMOVDQA instruction still requires its memory operand to be aligned.
Unlike their non-VEX coded counterparts, most VEX coded vector instructions no longer require their memory operands to be aligned to the vector size. The alignment requirement of SIMD memory operands is relaxed. VEX coding is also used for instructions operating on the k0-k7 mask registers that were introduced with AVX-512. It was later used for coding new instructions on general purpose registers in later extensions, such as BMI. Originally, AVX's three-operand format was limited to the instructions with SIMD operands (YMM), and did not include instructions with general purpose registers (e.g. For example, an SSE instruction using the conventional two-operand form a ← a + b can now use a non-destructive three-operand form c ← a + b, preserving both source operands. The legacy SSE instructions can be still utilized via the VEX prefix to operate on the lower 128 bits of the YMM registers.ĪVX-512 register scheme as extension from the AVX (YMM0-YMM15) and SSE (XMM0-XMM15) registersĪVX introduces a three-operand SIMD instruction format called VEX coding scheme, where the destination register is distinct from the two source operands. The width of the SIMD registers is increased from 128 bits to 256 bits, and renamed from XMM0–XMM7 to YMM0–YMM7 (in x86-64 mode, from XMM0–XMM15 to YMM0–YMM15).
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